Southern University of Science and Technology (SUSTech) is a public university founded in the Shenzhen Special Economic Zone of China.
SUSTech offers an unparalleled learning and research experience at the scientific and technological frontiers.
SUSTech offers unprecedented opportunities for undergraduate and graduate students to work alongside the faculty to explore and tackle both fundamental and practical problems.
The Global Engagement Office (GEO) is responsible for forming and implementing a coherent strategy to promote the University’s international development and global profile.
The undergraduate admission of SUSTech adopts comprehensive evaluation enrollment mode based on national college entrance examination.The graduate admission of SUSTech currently adopts joint training mode.
The main duties of SUSTCEF is to accept the donations from the domestic and foreign associations, enterprises, trading companies and individuals, and establish the funding projects depending on the demands of the university and the wishes of the donors.
PhD, National Univ of Singapore
Emerging Si-based Nano Electronic Device in the areas of both “More Moore” and “More than Moore”
1) Novel Non-Volatile Memory Research
2) Sub-22nm CMOS devices
3) Advanced Photovoltaic devices and CMOS photonics
4) Bio-sensor devices
◆ PhD, National University of Singapore, 2004
◆ M.ASc., University of Toronto, 2001
◆ B.Eng., Tsinghua University, 1999
Honors & Awards
◆ The Recruitment Program of Global Experts (Young Scholar Program), Organization Department of the CCCPC, 2011
◆ Kongque-plan Award, ShenZhen (2011)
◆ Nanyang Assistant Professorship, NTU, 2008
◆ Highlight paper in Symposium on VLSI Technology, 2007 (Kyoto, Japan)
◆ IEEE Electron Device Society (EDS) Graduate Fellowship 2004, USA
◆ Special allowance by the ShenZhen Municipal Government
◆ L. Y. Li, H.Y. Yu, et al, “Novel low aspect-ratio Si nano-hemisphere array surface texturing for solar cell applications”, Small, Vol. 7, pp. 3138-3143, January 2011
◆ S. M. Wong, H. Y. Yu, et al, “Boosting Short Circuit Current with Rationally Designed Periodic Si Nanopillar Surface Texturing for Solar Cells,” IEEE Transaction on Electron Devices, vol.58, no.9, pp.3224-3229, 2011
◆ S. M. Wong, H. Y. Yu, et al, “Design High Efficiency Si Nanopillar Array Textured Thin Film Solar Cell”, IEEE Electron Device Letter, Volume 31, pp.335-337, 2010
◆ J.S. Li, H.Y. Yu, et al, “Si nanopillar array optimization on Si thin films for solar energy harvesting,” Applied Physics Letter, Volume: 95 Issue: 3 Article Number: 033102 Published: JUL 20 2009, also selected Virtual Journal of Nanoscale Science & Technology, August 3, 2009
◆ Y. Sun, H.Y. Yu, N. Singh, E. Gnani, G. Baccarani, K. C. Leong, G.Q. Lo, D. L. Kwong, “Vertical Si-nanowire based Non-Volatile Memory with High Performance and Reduced Process Complexity,” IEEE Transaction on Electron Devices, vol. 58, pp.1329-1335, May 2011
◆ X.A. Tran, H.Y. Yu, et al, “Ni Electrode Unipolar Resistive RAM Performance Enhancement by AlOy Incorporation into HfOx Switching Dielectrics,” IEEE Electron Device Letter, vol 32 no. 9 pp. 1290-1292, spt. 2011
◆ Z. Fang, H. Y. Yu, et al, “HfOx/TiOx/HfOx/TiOx Multilayer Based Forming Free RRAM Devices with Excellent Uniformity,” IEEE Electron Device Letter, vol.32, pp.566-568, Apr. 2011
CMOS Devices and Graphene
◆ L. Wu, and H.Y. Yu, et al, “Device Performance and Reliability Improvement for MOSFETs with HfO2 Gate Dielectrics Fabricated using Multi Deposition Multi Room-Temperature Annealing,” IEEE Electron Device Letter, vol. 32, no.9, pp1173-1175, 2011
◆ W. J. Liu, H. Y. Yu, et al, “Understanding Asymmetric Transportation Behavior in Graphene Field Effect Transistors Using Scanning Kelvin Probe Microscopy,” IEEE Electron Device Letter, vol.32, pp.128-130, Feb. 2011
◆ Z. X. Chen, H. Y. Yu, et al, “Demonstration of tunneling FETs based on highly-scalable vertical silicon nanowires,” IEEE Electron Device Letter, Volume: 30 Issue: 7 Pages: 754-756 Published: JUL 2009